Minimizing Contamination For State-of-the-art Sample Analysis
By Pennington & Schoen
This article comes from our archive of more than 2,100 technical articles published since 1984. The article originally appeared in May 2010 and is being republished because it contains useful information that remains relevant.
Semiconductor geometries continue to shrink and ultrapure water (UPW*) guidelines continue to push quality requirements and analytical methods to lower levels in order to meet fab processing needs.
Sampling is the fundamental step of high-purity water testing and an appropriate, representative sample is critical for accurate results. Extremely low levels are only achieved by continually refining and improving our basic knowledge and understanding of sample collection. Sample valve design and set-up can be a significant hindrance to obtaining clean samples. At times, data is reported with a note indicating potentially false high hits due to suspected sampling contamination. False high data generates confusion for facilities operations personnel where port or environmental artifacts must be explained or rechecked to show the UPW system is or is not in compliance. It also wastes time and money due to resampling. Eliminating or minimizing false high hits is possible by investigating proper sample valve designs, set-up and preparation techniques.
Several sample valve types and configurations are available for high-purity application. This article will compare the most commonly used valves, and also discuss their proper installation and preparation. Selected case studies from the semiconductor industry will be reviewed. In addition to sampling at the point-of-distribution (POD), this article will also discuss field experience regarding the challenges of sampling highpurity water at the wafer point-of-entry (POE), and point-of-process (POP).
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