Behavior of Metal Deposition from High-Purity Water During Wafer Rinsing Process
By Drew Sinha, Ph.D., Jeff Chapman, and Richard Godec
The impact of metal contamination on semiconductor device yield is well established. Decreasing device size increases sensitivity to metal contamination. Furthermore, different metals often impact the device performance via different mechanisms. The International Technology Roadmap (ITRS) indicates that less than 1 part per trillion (ppt) level of critical metal in high-purity water (UPW*). Traditionally the wet cleaning process of silicon wafer is based on RCA-based wafer cleaning (1). Over the years, the process has been modified, or alternate cleaning processes have been developed.
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